SH7205 Datasheet, PDF (1345/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
• Multiword DMA timing register value table
Enhanced Bus Clock Mode 0
66 MHz
H'042F
Mode 1
H'0166
Mode 2
H'0126
(6) Ultra DMA timing register (ATAPI_ULTRA_TIMING)
Before accessing an ATAPI device, set the number of machine cycles in the following bits in this
register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
uSDCT
uSDRP
Initial value: ^-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14
-
-
Initial value: -
-
R/W: R
R
13 12
-
-
-
-
R
R
11 10
-
-
-
-
R
R
9
8
7
6
5
4
3
2
1
0
-
uMDCT
uMDRP
-
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 25 

R
Reserved
24 to 21 uSDCT
0000
R/W These bits specify the cycle time for a slave ATAPI
device.
20 to 16 uSDRP
00000
R/W These bits specify the time from the negation of
DMARDY (not IDEIORDY) until this module is
suspended by a slave ATAPI device.
15 to 9 

R
Reserved
8 to 5 uMDCT 0000
R/W These bits specify the cycle time for the master ATAPI
device.
4 to 0 uMDRP
00000
R/W These bits specify the time from the negation of
DMARDY (not IDEIORDY) until this module is
suspended by the master ATAPI device.
Note: The prefix uS pertains to slaves, and uM, to the master.
Rev. 1.00 Mar. 25, 2008 Page 1313 of 1868
REJ09B0372-0100