SH7205 Datasheet, PDF (459/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
• Unit operand transfer
DMA request
Interrupt request
DMATC_N
Transfer data
Operand 1
Byte count
Operand 2
Operand 3
• Sequential operand transfer
Channel arbitration
Channel arbitration
DMA request
Interrupt request
DMATC_N
Transfer data
Operand 1
Byte count
Operand 2
Operand 3
• Non-stop transfer
DMA request
Interrupt request
DMATC_N
Transfer data
Channel arbitration
Channel arbitration
Byte count
Figure 11.4 DMA Transfer Conditions
Rev. 1.00 Mar. 25, 2008 Page 427 of 1868
REJ09B0372-0100