SH7205 Datasheet, PDF (721/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 14 Watchdog Timer (WDT)
14.3.3 Watchdog Reset Control/Status Register (WRCSR0, WRCSR1)
WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal
generated by watchdog timer counter (WTCNT) overflow.
Note: The method for writing to WRCSR differs from that for other registers to prevent
erroneous writes. See section 14.3.4, Notes on Register Access, for details.
Bit: 7
6
5
4
3
2
1
0
WOVF RSTE RSTS -
-
-
-
-
Initial value: 0
0
*¹
1
1
1
1
1
R/W: R/(W) R/W R/W R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
7
WOVF
0
R/(W) Watchdog Timer Overflow
Indicates that the WTCNT has overflowed in watchdog
timer mode. This bit is not set in interval timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
[Clearing condition]
• When 0 is written to WOVF after reading WOVF
6
RSTE
0
R/W Reset Enable
Selects whether to generate a signal to reset the LSI
internally if WTCNT overflows in watchdog timer
mode. In interval timer mode, this setting is ignored.
0: Not reset when WTCNT overflows*²
1: Reset when WTCNT overflows
Rev. 1.00 Mar. 25, 2008 Page 689 of 1868
REJ09B0372-0100