SH7764 Datasheet, PDF (984/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
Initial
Value R/W Description
7 to 0 
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note:
Modify each bit in this register while CSSTS is 0 and PID is NAK. Before modifying each bit
after modifying the PID bits for the corresponding pipe from BUF to NAK, check that CSSTS
and PBUSY are 0. However, if the PID bits have been modified to NAK by this module,
checking PBUSY through software is not necessary.
21.3.38 PIPEn Transaction Counter Registers (PIPEnTRN) (n = 1 to 5)
PIPEnTRN is a transaction counter corresponding to PIPE1 to PIPE5.
This register is initialized by a power-on reset, but retains the set value by a USB bus reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TRNCNT[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
Initial
Value R/W
15 to 0 TRNCNT[15:0] All 0 R/W
Description
Transaction Counter
When written to:
Specifies the number of transactions to be
transferred through DMA.
When read from:
Indicates the specified number of transactions if
TRENB is 0.
Indicates the number of currently counted
transaction if TRENB is 1.
Rev. 1.00 Nov. 22, 2007 Page 928 of 1692
REJ09B0360-0100