SH7764 Datasheet, PDF (434/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
12.3.8 DMA Operation Register 0 (DMAOR0)
DMAOR0 is a 16-bit readable/writable register that specifies the priority level of channels at the
DMA transfer. This register shows the DMA transfer status. DMAOR0 is a common register for
channel 0 to 5.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CMS[1:0]
PR[1:0]
AE NMIF DME
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R/W R/W R R R/W R/W R R R R R R/(W)*R/(W)* R/W
Bit
15, 14
13, 12
11, 10
Initial
Bit Name Value
—
All 0
CMS[1:0] 00
—
All 0
R/W
R
R/W
R
Descriptions
Reserved
These bits are always read as 0. The write value should
always be 0.
Cycle Steal Mode Select
Select either normal mode or intermittent mode in cycle
steal mode.
It is necessary that all channel bus modes (for channels
0 to 5) are set to cycle steal mode to make valid
intermittent mode.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
Executes one DMA transfer in each of 16 clocks of
an external bus clock.
11: Intermittent mode 64
Executes one DMA transfer in each of 64 clocks of
an external bus clock.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 378 of 1692
REJ09B0360-0100