SH7764 Datasheet, PDF (724/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
9
PDTA
0
R/W Parallel Data Alignment
If the data word length is 32, 16 or 8 then this bit has no
meaning.
This bit is applied to SSIRDR0 to SSIRDR5 in receive
mode and to SSITDR0 to SSITDR05 in transmit mode.
0: Parallel data (SSITDR0 to SSITDR5 or SSIRDR0 to
SSIRDR5) is left aligned.
1: Parallel data (SSITDR0 to SSITDR5 or SSIRDR0 to
SSIRDR5) is right aligned.
• DWL[2:0] = 000 (data word length: 8 bits), PDTA
ignored
All data bits in SSITDR0 to SSITDR5 or SSIRDR0 to
SSIRDR5 are used on the audio serial bus. Four
data words are transmitted or received in each 32-
bit access. The first data word is stored in bits 7 to
0, the second in bits 15 to 8, the third in bits 23 to 16
and the last in bits 31 to 24.
• DWL[2:0] = 001 (data word length: 16 bits), PDTA
ignored
All data bits in SSITDR0 to SSITDR5 or SSIRDR0 to
SSIRDR5 are used on the audio serial bus. Two
data words are transmitted or received in each 32-
bit access. The first and second data words are
stored in bits 15 to 0 and bits 31 to 16, respectively.
• DWL[2:0] = 010, 011, 100, 101 (data word length:
18, 20, 22 and 24 bits), PDTA = 0 (left aligned)
The data bits which are used in SSITDR0 to
SSITDR5 or SSIRDR0 to SSIRDR5 are as follows:
Bits 31 to (32 – number of bits having data word
length specified by DWL[2:0]).
If DWL[2:0] = 011, then data word length is 20 bits
and bits 31 to 12 in SSITDR0 to SSITDR5 or
SSIRDR0 to SSIRDR5 are used. All other bits are
ignored or reserved.
Rev. 1.00 Nov. 22, 2007 Page 668 of 1692
REJ09B0360-0100