SH7764 Datasheet, PDF (1372/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
25.5 Interrupt Sources
The FLCTL has six interrupt sources: Status error, ready/busy timeout error, ECC error, transfer
end, FIFO0 transfer request, and FIFO1 transfer request. Each of the interrupt sources has its
corresponding interrupt flag and the interrupt can be requested independently to the CPU if the
interrupt is enabled by the interrupt enable bit. Note that the status error, ready/busy timeout error,
and ECC error use the common FLSTE interrupt to the CPU.
Table 25.5 FLCTL Interrupt Requests
Interrupt Source Interrupt Flag Enable Bit Description
Priority
FLSTE interrupt
STERB
STERINTE Status error
Highest
BTOERB
RBERINTE Ready/busy timeout error
ECERB
ECERINTE ECC error
FLTEND interrupt TREND
TEINTE
Transfer end
FLTRQ0 interrupt TRREQF0
TRINTE0
FIFO0 transfer request
FLTRQ1 interrupt TRREQF1
TRINTE1
FIFO1 transfer request
Lowest
Note: Flags for the FIFO0 overrun error/underrun error and FIFO1 overrun error/underrun error
also exist. However, no interrupt is requested to the CPU.
25.6 DMA Transfer Specifications
The FLCTL can request DMA transfers separately to the data area FLDTFIFO and control code
area FLECFIFO. Table 25.6 summarizes DMA transfer enable or disable states in each access
mode.
Table 25.6 DMA Transfer Specifications
FLDTFIFO
FLECFIFO
Sector Access Mode
DMA transfer enabled
DMA transfer enabled
Command Access Mode
DMA transfer enabled
DMA transfer disabled
For the setting of DMAC, see section 12, Direct Memory Access Controller (DMAC).
Rev. 1.00 Nov. 22, 2007 Page 1316 of 1692
REJ09B0360-0100