SH7764 Datasheet, PDF (829/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value R/W Description
4 to 0 RFD[4:0] B'00111 R/W Receive FIFO Size
Specifies the size of the receive FIFO. The setting must
not be changed after transmission/reception has
started.
00000: 256 bytes
00001: 512 bytes
00010: 768 bytes
00011: 1024 bytes
00100: 1280 bytes
00101: 1536 bytes
00110: 1792 bytes
00111: 2048 bytes
Other than above: Setting prohibited
Note: Operation cannot be guaranteed when the value set in this register is greater than the
transmit FIFO size.
20.2.12 Receiving Method Control Register (RMCR)
RMCR is a 32-bit readable/writable register that specifies the control method for the RE bit in
ECMR while a frame is received. This register must be set during the receiving-halted state.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
— RNC RNR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 773 of 1692
REJ09B0360-0100