SH7764 Datasheet, PDF (905/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
1
PIPE1NRDYE 0
R/W NRDY Interrupt Enable for PIPE1
0: Interrupt output disabled
1: Interrupt output enabled
0
PIPE0NRDYE 0
R/W NRDY Interrupt Enable for PIPE0
0: Interrupt output disabled
1: Interrupt output enabled
21.3.14 BEMP Interrupt Enable Register (BEMPENB)
BEMPENB is a register that enables or disables the BEMP bit in INTSTS0 to be set to 1 when the
BEMP interrupt is detected for each pipe.
On detecting the BEMP interrupt for the pipe corresponding to the bit in this register to which
software has set 1, this module sets 1 to the corresponding PIPEBEMP bit in BEMPSTS and the
BEMP bit in INTSTS0, and generates the BEMP interrupt.
While at least one PIPEBEMP bit in BEMPSTS indicates 1, this module generates the BEMP
interrupt when software modifies the corresponding interrupt enable bit in BEMPENB from 0 to 1.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
PIPE9 PIPE8 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0
BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 849 of 1692
REJ09B0360-0100