SH7764 Datasheet, PDF (1369/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
NAND-type flash memory (512 + 16 bytes)
Bit 17
Physical sector address
Bit 0 Note: FLADR2 is not used.
Bit 17
Physical sector address bit (FLADR[17:0])
Bit 0
Row3
Row2
Row3
000000
Row2
Row1
Row1
Order of address output to NAND-type flash memory I/O
Col
Row1
Row2
Row3
NAND-type flash memory (2048 + 64 bytes)
Bit 25
Physical sector address
Bit 25
Physical sector address bit (FLADR[25:0])
Row3
Row2
Row1
Col
00000000
[Legend]
CA: Column address
Row: Row address (page address)
Bit 0
Bit 0
Col
Note: FLADR[1:0] specify the boundary
address for column address in the
unit of 512 + 16 bytes.
When NAND-type flash memory
(2048 + 64 bytes) is used, set
FLADR[1:0] as follows.
00: 0 byte
01: 512 + 16 bytes
10: 1024 + 32 bytes
11: 1536 + 48 bytes
When ADRCNT2 = 0
Row2
Row1
Order of address output to NAND-type flash memory I/O
Col1
Col2
Row1
Row2
When ADRCNT2 = 1 (Bits[25:18] are valid.)
Row3
Col2
00000
Col1
0 00
[Legend]
CA: Column address
Row: Row address (page address)
0000
Note: When FADRCNT2 = 1, FLADR[25:18] are valid.
Set the invalid bit to 0 depending on the capacity of flash memory.
Order of address output to NAND-type flash memory I/O
Col1
Col2
Row1 Row1 Row3
Figure 25.10 Relationship between Sector Number and Address Expansion of
NAND-Type Flash Memory
Rev. 1.00 Nov. 22, 2007 Page 1313 of 1692
REJ09B0360-0100