SH7764 Datasheet, PDF (335/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.4.7 Arbitration Mode Register (AMR)
Bit: 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LAM[2:0]
       SWAM
Initial value: 0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R/W R/W R/W R R R R R R R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0

PAM[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R R R R/W R R
Initial
Bit
Bit Name Value R/W
63 to 27 
All 0 R
26 to 24 LAM2 to 100 R/W
LAM0
23 to 17 
All 0 R
16
SWAM 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
LCDC Arbitration Select
These bits set the arbitration priority level of the LCDC.
100: The arbitration priority of the LCDC is level 1
(default).
010: The arbitration priority of the LCDC is level 2.
001: The arbitration priority of the LCDC is level 3.
Reserved
These bits are always read as 0. The write value should
always be 0.
SuperHyway Module Level 2 Arbitration Enable
This bit sets the priority of the SuperHyway module to
level 2.
Rev. 1.00 Nov. 22, 2007 Page 279 of 1692
REJ09B0360-0100