SH7764 Datasheet, PDF (425/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
12.3.6 DMA Transfer Count Registers (TCRB0 to TCRB3)
TCRB are 32-bit readable/writable registers. Data to be written from the CPU to TCR is also
written to TCRB. While the half-end function is used, TCRB are used as the initial value hold
registers to detect HE. Also, TCRB specify the number of DMA transfers which are set in TCR in
repeat mode. TCRB specify the number of DMA transfers and are used as transfer count counters
in reload mode.
In reload mode, the lower 8 bits (bits 7 to 0) operate as transfer count counters, values of SAR and
DAR are updated after the value of bits 7 to 0 became 0, and then the value of bits 23 to 16 of
TCRB are loaded to bits 7 to 0. In bits 23 to 16, set the number of transferring until it reloads. In
reload mode, set the same number of transfers in both bits 23 to 16 and 7 to 0, and clear bits 15 to
8 to H’00. Also, clear the HIE bit in CHCR to 0 and do not use the half-end function.
The upper eight bits of TCRB (bits 31 to 24) are always read as 0, and the write value should
always be 0.
The initial value of TCRB is undefined.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCRB
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TCRB
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 369 of 1692
REJ09B0360-0100