SH7764 Datasheet, PDF (903/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
1
PIPE1BRDYE 0
R/W BRDY interrupt Enable for PIPE1
0: Interrupt output disabled
1: Interrupt output enabled
0
PIPE0BRDYE 0
R/W BRDY interrupt Enable for PIPE0
0: Interrupt output disabled
1: Interrupt output enabled
21.3.13 NRDY Interrupt Enable Register (NRDYENB)
NRDYENB is a register that enables or disables the NRDY bit in INTSTS0 to be set to 1 when the
NRDY interrupt is detected for each pipe.
On detecting the NRDY interrupt for the pipe corresponding to the bit in this register to which
software has set 1, this module sets 1 to the corresponding PIPENRDY bit in NRDYSTS and the
NRDY bit in INTSTS0, and generates the NRDY interrupt.
While at least one PIPENRDY bit in NRDYSTS indicates 1, this module generates the NRDY
interrupt when software modifies the corresponding interrupt enable bit in NRDYENB from 0 to
1.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
PIPE9 PIPE8 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0
NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 847 of 1692
REJ09B0360-0100