SH7764 Datasheet, PDF (249/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Memory Management Unit (MMU)
3. Sets exception code H'040 in the case of a read, or H'060 in the case of a write in EXPEVT
(OCBP, OCBWB: read; OCBI, MOVCA.L: write).
4. Sets the PC value indicating the address of the instruction at which the exception occurred in
SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the
delayed branch instruction in SPC.
5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are
saved in SGR.
6. Sets the MD bit in SR to 1, and switches to privileged mode.
7. Sets the BL bit in SR to 1, and masks subsequent exception requests.
8. Sets the RB bit in SR to 1.
9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and
starts the data TLB miss exception handling routine.
(2) Software Processing (Data TLB Miss Exception Handling Routine)
Software is responsible for searching the external memory page table and assigning the necessary
page table entry. Software should carry out the following processing in order to find and assign the
necessary page table entry.
1. In TLB compatible mode, write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT
bits in the page table entry stored in the address translation table for external memory.
In TLB extended mode, write to PTEL and PTEA the values of the PPN, EPR, ESZ, C, D, SH,
V, and WT bits in the page table entry stored in the address translation table for external
memory.
2. When the entry to be replaced in entry replacement is specified by software, write the value to
the URC bits in MMUCR. If URC is greater than URB at this time, the value should be
changed to an appropriate value after issuing an LDTLB instruction.
3. In TLB compatible mode, execute the LDTLB instruction and write the contents of PTEH and
PTEL to the TLB.
In TLB extended mode, execute the LDTLB instruction and write the contents of PTEH,
PTEL, PTEA to the UTLB.
4. Finally, execute the exception handling return instruction (RTE), terminate the exception
handling routine, and return control to the normal flow. The RTE instruction should be issued
at least one instruction after the LDTLB instruction.
For the execution of the LDTLB instruction, see section 7.8.1, Note on Using LDTLB Instruction.
Rev. 1.00 Nov. 22, 2007 Page 193 of 1692
REJ09B0360-0100