SH7764 Datasheet, PDF (715/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Bit
11
10
9
8
7 to 5
Bit Name
BLKNEND1
(BLKNEND4)
Initial
Value
0
DMEND1
0
(DMEND4)
TXFIFOFUL1 0
(TXFIFOFUL4)
RXFIFOEMP1 1
(RXFIFOEMP4)

All 0
R/W Description
R/W n-Times Block Transfer End 1 (4)
Indicates that data transfer whose block count is
specified by SSIBLNCNTSR1 (4) has been completed.
0: Indicates that data transfer whose block count is
specified by SSIBLNCNTSR1 (4) has not been
completed.
1: Indicates that data transfer whose block count is
specified by SSIBLNCNTSR1 (4) has been
completed.
R/W Transfer End 1 (4)
Indicates that data transfer whose word count is
specified by SSIRDMCNTR1 (4) or SSIWDMCNTR1 (4)
has been completed.
0: Indicates that data transfer whose word count is
specified by SSIRDMCNTR1 (4) or SSIWDMCNTR1
(4) has not been completed.
1: Indicates that data transfer whose word count is
specified by SSIRDMCNTR1 (4) or SSIWDMCNTR1
(4) has been completed.
R/W Transmit FIFO Full 1 (4)
Indicates that the transmit FIFO buffer for SSI_CH1
(CH4) is full.
0: Indicates that the transmit FIFO buffer for SSI_CH1
(CH4) is not full.
1: Indicates that the transmit FIFO buffer for SSI_CH1
(CH4) is full.
R/W Receive FIFO Empty 1 (4)
Indicates that the receive FIFO buffer for SSI_CH1
(CH4) is empty.
0: Indicates that the receive FIFO buffer for SSI_CH1
(CH4) is not empty.
1: Indicates that the receive FIFO buffer for SSI_CH1
(CH4) is empty.
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 659 of 1692
REJ09B0360-0100