SH7764 Datasheet, PDF (44/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Figure 33.48 Ultra-DMA Data Out-burst Start............................................................................1628
Figure 33.49 Ultra-DMA Data Out-burst ....................................................................................1629
Figure 33.50 Ultra-DMA Data Out-burst from Device Pause .....................................................1629
Figure 33.51 End of Ultra-DMA Data Out-burst from Host ........................................................1630
Figure 33.52 End of Ultra-DMA Data Out-burst from Device....................................................1631
Figure 33.53 PIO Data Transmission (DIRECTIO) to Device ....................................................1632
Figure 33.54 PIO Data Transmission (DIRECTIO) from Device ...............................................1632
Figure 33.55 Multiword DMA Transmission (DIRECTION) .....................................................1633
Figure 33.56 Ultra-DMA Transmission Data In-burst Start(DIRECTION) ................................1634
Figure 33.57 End of Ultra-DMA Transmission Data In-burst from Device (DIRECTION).......1635
Figure 33.58 End of Ultra-DMA Transmission Data In-burst from Host (DIRECTION)...........1636
Figure 33.59 Ultra-DMA Transmission Data Out-burst Start (DIRECTION) ............................1637
Figure 33.60 End of Ultra-DMA Transmission Data Out-burst from Host (DIRECTION) ........1638
Figure 33.61 End of Ultra-DMA Transmission Data Out-burst from Device (DIRECTION) ....1639
Figure 33.62 USB Clock Timing.................................................................................................1640
Figure 33.63 GPIO Timing..........................................................................................................1641
Figure 33.64 TCK Input Timing..................................................................................................1642
Figure 33.65 PRESET Hold Timing............................................................................................1643
Figure 33.66 H-UDI Data Transmission Timing.........................................................................1643
Figure 33.67 ASEBRKAK/BRKACK Pin Break Timing ...........................................................1643
Figure 33.68 MII Transmission Timing (during Normal Operation) ..........................................1645
Figure 33.69 MII Transmission Timing (in the Event of a Collision) .........................................1645
Figure 33.70 MII Receive Timing (during Normal Operation) ................................................... 1646
Figure 33.71 MII Receive Timing (in the Event of a Collision)..................................................1646
Figure 33.72 MDIO Input Timing ................................................................................................1646
Figure 33.73 MDIO Output Timing ............................................................................................1646
Figure 33.74 WOL Output Timing ..............................................................................................1647
Figure 33.75 EXOUT Output Timing..........................................................................................1647
Figure 33.76 NAND Flush Memory Command Issue Timing ....................................................1649
Figure 33.77 NAND Flush Memory Address Issue Timing........................................................1649
Figure 33.78 NAND Flush Memory Data Read Timing ............................................................1650
Figure 33.79 NAND Flush Memory Data Write Timing.............................................................1650
Figure 33.80 NAND Flush Memory Status Read Timing ...........................................................1651
Figure 33.81 LCDC Module Signal Timing ................................................................................1653
Figure 33.82 Clock Input/Output Timing ....................................................................................1654
Figure 33.83 VDC2 Transmission Timing (1).............................................................................1655
Figure 33.84 VDC2 Transmission Timing (2).............................................................................1655
Figure 33.85 VDC2 Reception Timing (1) .................................................................................1655
Figure 33.86 VDC2 Reception Timing (2).................................................................................1656
Figure 33.87 Output Load Circuit ...............................................................................................1657
Rev. 1.00 Nov. 22, 2007 Page xliv of lvi