SH7764 Datasheet, PDF (1487/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Watchdog Timer and Reset
Bit
5
4
3
2 to 0
Initial
Bit Name Value R/W

0

WOVF
0
R/W
IOVF
0
R/W

R
All 0
Description
Reserved
This bit is always read as 0. The write value should
always be 0
Watchdog Timer Overflow Flag
Indicates that WDTCNT has overflowed in watchdog
timer mode. This flag is not set in interval timer mode.
0: An overflow has not occurred
1: An overflow on WDTCNT has occurred
Interval Timer Overflow Flag
Indicates that WDTCNT has overflowed in interval
timer mode. This flag is not set in watchdog timer
mode.
0: An overflow has not occurred
1: An overflow on WDTCNT has occurred
Reserved
These bits are always read as 0. The write value
should always be 0.
29.3.3 Watchdog timer Base Stop Time Register (WDTBST)
WDTBST is a readable/writable 32-bit register that clears WDTBCNT. Use a longword write
access to clear the WDTBCNT, with H'55 in the bits 31 to 24. The reading value of this register is
always H'00.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
(Given code)
 
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Rev. 1.00 Nov. 22, 2007 Page 1431 of 1692
REJ09B0360-0100