SH7764 Datasheet, PDF (317/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Table 11.2 External Memory Space Map
Area External Address
Connectable
Size
Memory
0
H'0000 0000 to H'03FF FFFF 64 Mbytes SRAM
1
H'0400 0000 to H'07FF FFFF 64 Mbytes SDRAM
2
H'0800 0000 to H'0BFF FFFF 64 Mbytes SDRAM
3
H'0C00 0000 to H'0FFF FFFF 64 Mbytes SRAM
Notes: 1. The memory bus width is specified by external pins.
2. The memory bus width is specified by the register.
Specifiable
Access
Bus Width (Bit) Size
8, 16, 32*¹
8, 16, 32
32, 64*²
32, 64
32, 64*²
32, 64
8, 16, 32*²
8, 16, 32
11.3.2 Memory Bus Width
The memory bus width is set differently for each area. For area 0, a bus width of 8, 16, or 32 bits
is set according to the external pin settings at a power-on reset by the PRESET pin. The
correspondence between the external pins (MODE4 and MODE3) and the bus width is shown in
table 11.3.
Table 11.3 MODE Pin Settings for Memory Bus Width of Area 0
MODE4
0
0
1
1
MODE3
0
1
0
1
Bus Width
Reserved
8 bits
16 bits
32 bits
For areas 1 and 2, a bus width of 32 or 64 bits can be selected through the memory interface mode
register (MIM) (the bus width is same for areas 0 and 1). For details, see section 11.4.2, Memory
Interface Mode Register (MIM).
For area 3, a bus width of 8, 16, or 32 bits can be selected through the CS3 bus control register
(CS3BCR). For details, see section 11.4.15, CS3 Bus Control Register (CS3BCR).
Rev. 1.00 Nov. 22, 2007 Page 261 of 1692
REJ09B0360-0100