SH7764 Datasheet, PDF (1026/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
FIFO Port
Buffer Memory
CFIFO Port
CURPIPE = 6
D0FIFO Port
D1FIFO Port
CURPIPE = 1
CURPIPE = 3
PIPE0
PIPE6
PIPE7
PIPE5
PIPE1
PIPE2
PIPE3
PIPEBUF registers
BUFNMB = 0, BUFSIZE = 3
BUFNMB = 4, BUFSIZE = 0
BUFNMB = 5, BUFSIZE = 0
BUFNMB = 6, BUFSIZE = 3
BUFNMB = 10, BUFSIZE = 7
BUFNMB = 18, BUFSIZE = 3
BUFNMB = 22, BUFSIZE = 7
PIPE4
BUFNMB = 28, BUFSIZE = 2
Figure 21.9 Example of a Buffer Memory Map
(a) Buffer Status
Tables 21.19 and 21.20 show the buffer status. The buffer memory status can be confirmed using
the BSTS bit in DCPCTR and the INBUFM bit in PIPEnCTR. The access direction for the buffer
memory can be specified using either the DIR bit in PIPEnCFG or the ISEL bit in CFIFOSEL
(when DCP is selected).
The INBUFM bit is valid for PIPE0 to PIPE5 in the sending direction.
For an IN pipe uses double buffer, software can refer the BSTS bit to monitor the buffer memory
status of CPU side and the INBUFM bit to monitor the buffer memory status of SIE side. In the
case like the BEMP interrupt may not shows the buffer empty status because the CPU (DMAC)
writes data slowly, software can use the INBUFM bit to confirm the end of sending.
Rev. 1.00 Nov. 22, 2007 Page 970 of 1692
REJ09B0360-0100