SH7764 Datasheet, PDF (1074/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 22 LCD Controller (LCDC)
22.3.8 Palette Data Registers 00 to FF (LDPR00 to LDPRFF)
LDPR registers are for accessing palette data directly allocated (4 bytes x 256 addresses) to the
memory space. To access the palette memory, access the corresponding register among this
register group (LDPR00 to LDPRFF). Each palette register is a 32-bit register including three 8-bit
areas for R, G, and B. For details on the color palette specifications, see section 22.4.2, Color
Palette Specification.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16








PALDnn[23:16]
Initial value: 















R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
Initial value: 
R/W: R/W
14

R/W
13

R/W
12

R/W
11

R/W
10

R/W
9

R/W
8
7
PALDnn[15:0]


R/W R/W
6

R/W
5

R/W
4

R/W
3

R/W
2

R/W
1

R/W
0

R/W
Bit
Bit Name Initial Value R/W
31 to 24 

R
23 to 0 PALDnn[23:0] 
R/W
Note: nn = H'00 to H'FF
Description
Reserved
Palette Data
Bits 18 to 16, 9, 8, and 2 to 0 are reserved within
each RGB palette and cannot be set. However,
these bits can be extended according to the upper
bits.
Rev. 1.00 Nov. 22, 2007 Page 1018 of 1692
REJ09B0360-0100