SH7764 Datasheet, PDF (646/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
Table 17.3 ATAPI Packet Command Task File Register Map
(These resisters are allocated to the ATAPI or ATA device, and are not allocated to this module.)
Address
Read Register
Write Register
Pin Address Access Size*¹
(IDECS[1:0], (Available Bit Register
IDEA[2:0]) Size)
Location
H'FFF0 0000 Data
Data
HL-LLL
32 (16)*²
Drive
H'FFF0 0004 Error
Function
HL-LLH
32 (8)*³
Drive
H'FFF0 0008 Interrupt source —
HL-LHL
32 (8)*³
Drive
H'FFF0 000C —
—
HL-LHH
32 (8)*³
Drive
H'FFF0 0010 Byte Count Low Byte Count Low HL-HLL
32 (8)*³
Drive
H'FFF0 0014 Byte Count High Byte Count High HL-HLH
32 (8)*³
Drive
H'FFF0 0018 Device select Device select
HL-HHL
32 (8)*³
Drive
H'FFF0 001C Status
Command
HL-HHH
32 (8)*³
Drive
H'FFF0 0038 Alternate Status Device Control LH-HHL
32 (8)*³
Drive
Notes: 1. These registers must be accessed in longwords (32 bits) by the CPU. Byte or word
accesses are prohibited.
2. Bits 15 to 0 of the data bus are used.
3. Bits 7 to 0 of the data bus are used.
Rev. 1.00 Nov. 22, 2007 Page 590 of 1692
REJ09B0360-0100