SH7764 Datasheet, PDF (449/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
(2) Bus Modes
There are two bus modes: cycle steal mode and burst mode. Select the mode in the TB and LCKN
bits in CHCR. And cycle steal mode has normal and intermittent modes that are specified by the
CMS bits in DMAOR.
• Cycle-Steal Mode
 Normal mode1 (CHCR.LCKN = 0, CHCR.TB = 0)
In cycle-steal normal mode, the SuperHyway bus mastership is given to another bus master
after a one-transfer unit (byte, word, longword, 16-byte, or 32-byte unit) DMA transfer.
When the next transfer request occurs, the DMAC issues the next transfer request, the bus
mastership is obtained from the other bus master and a transfer is performed for one-
transfer unit. When that transfer ends, the bus mastership is passed to the other bus master.
This is repeated until the transfer end conditions are satisfied.
In cycle-steal normal mode, transfer areas are not affected regardless of settings of the
transfer request source, transfer source, and transfer destination.
Figure 12.6 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer
conditions shown in the figure are:
DREQ
SuperHyway
bus cycle
Bus mastership returned to CPU once
CPU
CPU
CPU
DMAC DMAC
Read/Write
CPU DMAC DMAC CPU
Read/Write
Figure 12.6 DMA Transfer Timing Example in Cycle-Steal Normal Mode 1
(DREQ Low Level Detection)
 Normal mode 2 (CHCR.LCKN = 1, CHCR.TB = 0)
In cycle steal normal mode 2, the DMAC does not keep the SuperHyway bus mastership, is
to obtain the bus mastership in every one transfer unit of read or write cycle.
Figure 12.7 shows an example of DMA transfer timing in cycle steal normal mode 2.
Rev. 1.00 Nov. 22, 2007 Page 393 of 1692
REJ09B0360-0100