SH7764 Datasheet, PDF (1377/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 Sampling Rate Converter (SRC)
26.2.2 SRC Output Data Register (SRCOD)
SRCOD is a 32-bit read-only register used to output the data after sampling rate conversion. The
data in 8-stage output data FIFO is read through SRCOD.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³ 0* ³
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
The data in SRCOD is aligned differently depending on the OCH and OED bit setting in
SRCODCTRL. Table 26.4 shows the correspondence between the OCH and OED bit setting and
data alignment in SRCOD.
Table 26.4 Alignment of Data in SRCOD
OCH OED SRCOD[31:24] SRCOD[23:16] SRCOD[15:8] SRCOD[7:0]
0
0
ch0[15:8]
ch0[7:0]
ch1[15:8]*²
ch1[7:0]*²
1
ch0[7:0]
ch0[15:8]
ch1[7:0]*²
ch1[15:8]*²
1*¹
0
ch1[15:8]
ch1[7:0]
ch0[15:8]
ch0[7:0]
1
ch1[7:0]
ch1[15:8]
ch0[7:0]
ch0[15:8]
Notes: 1. When processing monaural data, do not set the bit to 1.
2. When processing monaural data, the data in these bits is invalid.
3. If the CL bit in the SRCCTRL register is read after 1 is written to it, it is read as 0. If the
CL bit is read before 1 is written to it, the read value cannot be guaranteed.
Rev. 1.00 Nov. 22, 2007 Page 1321 of 1692
REJ09B0360-0100