SH7764 Datasheet, PDF (324/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Initial
Bit
Bit Name Value R/W
63 to 48 
All 0 R
47, 46 BOMODE1 00
R/W
and
BOMODE0
45

0
R
44
PCKE
0
R/W
43 to 35 
All 0 R
34
SELFS 0
R
33
RMODE 0
R/W
32 to 28 
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
These bits are readable/writable bits that select the
SDRAM access mode. The MCU supports two SDRAM
access modes. For details on the operation in each
mode, see section 11.7.7, Bank Open Mode.
00: Bank open mode
01: Bank close mode
Other than above: Setting prohibited
Reserved
This bit is always read as 0. The write value should
always be 0.
Setting this bit to 1 sets the CKE pin low and places the
MCU in power-down mode when the SDRAM is not
accessed (in the idle state or bank active state). This
function can reduce power consumption of the SDRAM.
Reserved
These bits are always read as 0. The write value should
always be 0.
This bit indicates whether the SDRAM is in the self-
refresh state. A value of 1 indicates that the SDRAM is
in the self-refresh state, and a value of 0 indicates that
it is not in the self-refresh state.
This readable/writable bit specifies whether to perform
auto-refreshing or self-refreshing. The bit is valid only
when the DRE bit is set to 1.
0: Auto-refreshing
1: Self-refreshing
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 268 of 1692
REJ09B0360-0100