SH7764 Datasheet, PDF (12/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 8 Caches................................................................................................ 207
8.1 Features.............................................................................................................................. 207
8.2 Register Descriptions......................................................................................................... 211
8.2.1 Cache Control Register (CCR) ............................................................................. 212
8.2.2 Queue Address Control Register 0 (QACR0)....................................................... 214
8.2.3 Queue Address Control Register 1 (QACR1)....................................................... 215
8.2.4 On-Chip Memory Control Register (RAMCR) .................................................... 216
8.3 Operand Cache Operation.................................................................................................. 218
8.3.1 Read Operation ..................................................................................................... 218
8.3.2 Prefetch Operation ................................................................................................ 219
8.3.3 Write Operation .................................................................................................... 220
8.3.4 Write-Back Buffer ................................................................................................ 221
8.3.5 Write-Through Buffer........................................................................................... 221
8.3.6 OC Two-Way Mode ............................................................................................. 222
8.4 Instruction Cache Operation .............................................................................................. 223
8.4.1 Read Operation ..................................................................................................... 223
8.4.2 Prefetch Operation ................................................................................................ 223
8.4.3 IC Two-Way Mode............................................................................................... 224
8.4.4 Instruction Cache Way Prediction Operation ....................................................... 224
8.5 Cache Operation Instruction .............................................................................................. 225
8.5.1 Coherency between Cache and External Memory ................................................ 225
8.5.2 Prefetch Operation ................................................................................................ 227
8.6 Memory-Mapped Cache Configuration ............................................................................. 228
8.6.1 IC Address Array.................................................................................................. 228
8.6.2 IC Data Array ....................................................................................................... 230
8.6.3 OC Address Array ................................................................................................ 230
8.6.4 OC Data Array...................................................................................................... 232
8.6.5 Memory-Mapped Cache Associative Write Operation......................................... 233
8.7 Store Queues ...................................................................................................................... 234
8.7.1 SQ Configuration.................................................................................................. 234
8.7.2 Writing to SQ........................................................................................................ 234
8.7.3 Transfer to External Memory ............................................................................... 235
8.7.4 Determination of SQ Access Exception................................................................ 236
8.7.5 Reading from SQ .................................................................................................. 236
Section 9 On-Chip Memory .............................................................................. 237
9.1 Features.............................................................................................................................. 237
9.2 Register Descriptions......................................................................................................... 238
9.2.1 On-Chip Memory Control Register (RAMCR) .................................................... 239
9.3 Operation ........................................................................................................................... 241
Rev. 1.00 Nov. 22, 2007 Page xii of lvi