SH7764 Datasheet, PDF (768/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
Initial
Bit
Bit Name Value R/W Description
1
MPDIP 0
R/W Magic Packet Detect Interrupt Enable
0: Interrupt notification by the MPD bit is disabled
1: Interrupt notification by the MPD bit is enabled
0
ICDIP
0
R/W Illegal Carrier Detect Interrupt Enable
0: Interrupt notification by the ICD bit is disabled
1: Interrupt notification by the ICD bit is enabled
19.3.4 PHY Interface Register (PIR)
PIR is a 32-bit readable/writable register that provides a means of accessing the PHY-LSI internal
registers via the MII.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
— MDI MDO MMD MDC
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
—
0
0
0
R/W: R R R R R R R R R R R R R R/W R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 4 
All 0
R
3
MDI
Undefined R
2
MDO
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
MII Management Data-In
Indicates the level of the MDIO pin.
MII Management Data-Out
Outputs the value set in this bit from the MDIO pin when
the MMD bit is 1.
Rev. 1.00 Nov. 22, 2007 Page 712 of 1692
REJ09B0360-0100