SH7764 Datasheet, PDF (1522/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 User Break Controller (UBC)
• When the Match Condition is Satisfied at the Instruction Fetch Cycle for Both the First and
Second Channels in the Sequence:
Instruction B is 0 instruction after instruction A Equivalent to setting the same addresses; do
not use this setting.
Instruction B is one instruction after instruction A Sequential operation is not guaranteed.
Instruction B is two or more instructions after
instruction A
Sequential operation is guaranteed.
• When the match condition is satisfied at the instruction fetch cycle for the first channel in the
sequence whereas the match condition is satisfied at the operand access cycle for the second
channel in the sequence:
Instruction B is 0 or one instruction after
instruction A
Instruction B is two or more instructions after
instruction A
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
• When the match condition is satisfied at the operand access cycle for the first channel in the
sequence whereas the match condition is satisfied at the instruction fetch cycle for the second
channel in the sequence:
Instruction B is 0 to five instructions after
instruction A
Instruction B is six or more instructions after
instruction A
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
• When the match condition is satisfied at the operand access cycle for both the first and second
channels in the sequence:
Instruction B is 0 to five instructions after
instruction A
Instruction B is six or more instructions after
instruction A
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
Rev. 1.00 Nov. 22, 2007 Page 1466 of 1692
REJ09B0360-0100