SH7764 Datasheet, PDF (489/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
Initial
Bit Bit Name Value
R/W Function
Description
15 SSI_ACH0 Undefined R
14 SSI_A
DMA0
13 G2D
12 to —
9
8
DMAC
Undefined R
Undefined R
All 0
R
Undefined R
7
H-UDI
6
—
5
WDT
4
SCIF1
3
SCIF0
Undefined R
0
R
Undefined R
Undefined R
Undefined R
Indicates SSI_A (SSICH0)
Indicates interrupt
interrupt source
sources for each
Indicates SSI_A (SSIDMA0)
interrupt source
Indicates G2D interrupt source
peripheral module
(INT2A0 is not affected
by the state of the
interrupt mask
Reserved
register).
These bits are always read as 0. ^{0: No interrupts}
Indicates DMAC channels 0 to 5
interrupt source and address error
1: Interrupts are
generated
interruption
Note: Reading the
Indicates H-UDI interrupt source
INTEVT code
notified to the
Reserved
CPU directly can
This bit is always read as 0..
Indicates WDT interrupt source
identify interrupt
sources. In this
case, reading
Indicates SCIF1 interrupt source
Indicates SCIF0 interrupt source
INT2A0 is not
necessary.
2
—
0
R Reserved
This bit is always read as 0.
1
TMU1
Undefined R Indicates TMU1 interrupt source
0
TMU0
Undefined R Indicates TMU0 interrupt source
Rev. 1.00 Nov. 22, 2007 Page 433 of 1692
REJ09B0360-0100