SH7764 Datasheet, PDF (120/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 3 Instruction Set
Instruction
XOR #imm,R0
Operation
R0 ∧ imm → R0
XOR.B #imm, @(R0,GBR) (R0 + GBR) ∧ imm →
(R0 + GBR)
Instruction Code
Privileged T Bit New
11001010iiiiiiii —
—
—
11001110iiiiiiii —
—
—
Table 3.7 Shift Instructions
Instruction
Operation
ROTL Rn
T ← Rn ← MSB
ROTR Rn
LSB → Rn → T
ROTCL Rn
T ← Rn ← T
ROTCR Rn
T → Rn → T
SHAD
Rm,Rn When Rm ≥ 0, Rn << Rm → Rn
When Rm < 0, Rn >> Rm →
[MSB → Rn]
SHAL Rn
T ← Rn ← 0
SHAR Rn
MSB → Rn → T
SHLD
Rm,Rn When Rm ≥ 0, Rn << Rm → Rn
When Rm < 0, Rn >> Rm →
[0 → Rn]
SHLL Rn
T ← Rn ← 0
SHLR Rn
0 → Rn → T
SHLL2 Rn
Rn << 2 → Rn
SHLR2 Rn
Rn >> 2 → Rn
SHLL8 Rn
Rn << 8 → Rn
SHLR8 Rn
Rn >> 8 → Rn
SHLL16 Rn
Rn << 16 → Rn
SHLR16 Rn
Rn >> 16 → Rn
Instruction Code Privileged T Bit
0100nnnn00000100 —
MSB
0100nnnn00000101 —
LSB
0100nnnn00100100 —
MSB
0100nnnn00100101 —
LSB
0100nnnnmmmm1100 —
—
0100nnnn00100000 —
0100nnnn00100001 —
0100nnnnmmmm1101 —
MSB
LSB
—
0100nnnn00000000 —
0100nnnn00000001 —
0100nnnn00001000 —
0100nnnn00001001 —
0100nnnn00011000 —
0100nnnn00011001 —
0100nnnn00101000 —
0100nnnn00101001 —
MSB
LSB
—
—
—
—
—
—
New
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Rev. 1.00 Nov. 22, 2007 Page 64 of 1692
REJ09B0360-0100