SH7764 Datasheet, PDF (1252/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
(5) Interrupt Command ID Register (ICIDR)
Offset:
H'010
Initial Value: Undefined
The interrupt command ID register (ICIDR) is a 32-bit read-only register used to store the ID
specified by the rendering attribute if the rendering attribute INT bit is set to 1 when the NOP/INT
command is fetched. The unused bits are always read as 0. ICIDR retains its value at a reset.
Bits 7 to 0—Interrupt Command ID
Bits 31 to 8—Reserved: These bits are always read as 0.
23.3.2 Memory Control Registers
(1) Return Address Register 0 (RTN0R)
Offset:
H'040
Initial Value: Undefined
The return address register 0 (RTN0R) is a 32-bit read-only register which stores the return
address when the rendering attribute No bit is 0 in the GOSUB command. The address indicated
by RTN0R is a longword address (bits A28 to A2). RTN0R retains its value at a reset. (The
unused bits are always read as undefined values.)
(2) Return Address Register 1 (RTN1R)
Offset:
H'044
Initial Value: Undefined
The return address register 1 (RTN1R) is a 32-bit read-only register which stores the return
address when the rendering attribute No bit is 1 in the GOSUB command. The address indicated
by RTN1R is a longword address (bits A28 to A2). RTN1R retains its value at a reset. (The
unused bits are always read as undefined values.)
(3) Display List Start Address Register (DLSAR)
Offset:
H'048
Initial Value: Undefined
Rev. 1.00 Nov. 22, 2007 Page 1196 of 1692
REJ09B0360-0100