SH7764 Datasheet, PDF (1326/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.24 SGDE Area Size Register (SGDESIZE)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16






SGDE_HEIGHT[9:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0





SGDE_WIDTH[10:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 26 
Initial
Value R/W
All 0 R
25 to 16 SGDE_HEIGHT H'000 R/W
[9:0]
15 to 11 
All 0 R
10 to 0 SGDE_WIDTH H'000 R/W
[10:0]
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
These bits specify the vertical length (height) of the
data enable (DE) signal area in number of lines.
Reserved
These bits are always read as 0. The write value
should always be 0.
These bits specify the horizontal length (width) of
the data enable (DE) signal area in number of
panel clock cycles.
Rev. 1.00 Nov. 22, 2007 Page 1270 of 1692
REJ09B0360-0100