SH7764 Datasheet, PDF (395/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

11.8 Wait Cycles between Accesses
Section 11 Memory Controller Unit (MCU)
11.8.1 Wait Cycles between Accesses to Area 0 or 3
The specified number of idle cycles are inserted between consecutive accesses to area 0 or area 3,
or between an access to area 0 or area 3 and the subsequent access to area 1 or area 2. The number
of idle cycles to be inserted is determined by the CSn bus control register (CSnBCR) and bus
control register (BCR).
Specifically, the bits IWW, IWRWD, IWRWS, IWRRD, and IWRRS in CSnBCR and the IRSD
bits in BCR are used to specify the number of wait cycles to be inserted as the idle cycle. Here, at
least the specified number of cycles are inserted.
Between an access to area 0 or area 3 and the subsequent access to area 1 or area 2, at least four
idle cycles are inserted. In addition, when the access size is 8 bytes, 16 bytes, or 32 bytes, wait
cycles are inserted every 4-byte access.
11.8.2 Wait Cycles between Accesses to Area 1 or 2
With respect to the consecutive accesses to area 1 or 2, the same area can be consecutively
accessed with an interval of one idle cycle (minimum) between the read and read commands or
between the write and write commands. In case of the write command followed by read command
or the read command followed by the write command, the same area is consecutively accessed
with the specified interval between the commands. Here, the interval is specified by the WR or
RW bits in the SDRAM timing register (STR).
Between consecutive accesses to area 1 and area 2, at least three idle cycles are inserted.
11.8.3 Wait Cycles between Access to Area 1 or 2 and the Subsequent Access to
Area 0 or 3
Between an access to area 1 or 2 and the subsequent access to area 0 or 3, at least two idle cycles
are inserted.
Rev. 1.00 Nov. 22, 2007 Page 339 of 1692
REJ09B0360-0100