SH7764 Datasheet, PDF (1508/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
1
PCB
0
R/W PC Break Select
Specifies either before or after instruction execution as
the break timing for the instruction fetch cycle. This bit
is invalid for breaks other than the ones for the
instruction fetch cycle.
0: Sets the PC break before instruction execution.
1: Sets the PC break after instruction execution.
0
BIE
0
R/W Break Enable
Specifies whether or not to request a break when the
match condition is satisfied for the channel.
0: Does not request a break.
1: Requests a break.
• CRR1
Bit : _{31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16}
Initial value : ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: _{R R R R R R R R R R R R R R R R}
Bit : _{15 14 13 12 11 10 9}
8
7
6
5
4
3
2
1
0
PCB BIE
Initial value : ₀
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: _{R R R R R R R R R R R R R R R/W R/W}
Bit
Bit Name
31 to 14 —
13
—
12 to 2 —
Initial
Value
All 0
1
All 0
R/W Description
R Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
R Reserved
This bit is always read as 1. The write value should
always be 1.
R Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
Rev. 1.00 Nov. 22, 2007 Page 1452 of 1692
REJ09B0360-0100