SH7764 Datasheet, PDF (256/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Memory Management Unit (MMU)
7.7.3 ITLB Data Array (TLB Extended Mode)
In TLB extended mode the names of the data arrays have been changed from ITLB data array to
ITLB data array 1, ITLB data array 2 is added, and the EPR and ESZ bits are accessible. In TLB
extended mode, the PR and SZ bits of ITLB data array 1 are reserved and 0 should be specified as
the write value for these bits. In addition, when a write to ITLB data array 1 is performed, a write
to ITLB data array 2 of the same entry should always be performed.
In TLB compatible mode (MMUCR.ME = 0), ITLB data array 2 cannot be accessed. Operation if
they are accessed is not guaranteed.
(1) ITLB Data Array 1
In TLB extended mode, bits 7, 6, and 4 in the data field, which correspond to the PR and SZ bits
in compatible mode, are reserved. Specify 0 as the write value for these bits.
31
23 22
10 9 8 7
210
Address field _{1 1 1 1 0 0 1 1 0 * * * * * * * * * * * * * E * * * * * * 0 0}
31 29 28
Data field
[Legend]
PPN: Physical page number
V: Validity bit
E: Entry
*: Don't care
PPN
10 9 8 7
V
C: Cacheability bit
SH: Share status bit
: Reserved bits
(write value should be 0,
and read value is undefined)
43210
C
SH
Figure 7.20 Memory-Mapped ITLB Data Array 1 (TLB Extended Mode)
Rev. 1.00 Nov. 22, 2007 Page 200 of 1692
REJ09B0360-0100