SH7764 Datasheet, PDF (735/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
• Number of channels
Six channels corresponding to SSI_CH0 to SSI_CH5 transmitters and receivers
• Transferred data size
8, 16 or 32 bytes
• Maximum transfer byte count
4,294,967,296 bytes
• Bus mode
Cycle-steal mode
• Priority order among channels
Fixed-order or round-robin can be selected for SSI_CH0 to SSI_CH2 and SSI_CH3 to
SSI_CH5.
• Transmit FIFO buffers and receive FIFO buffers
Transmit and receive FIFO buffers (32 bits x 16 stages) are provided for SSI_CH0 to
SSI_CH5.
• Interrupt requests
Block transfer end interrupt
n-times block transfer end interrupt
Transfer end interrupt
Transmit FIFO buffer full interrupt
Receive FIFO buffer empty interrupt
• Software reset
A software reset can be executed separately for SSI_CH0 to SSI_CH5. Each of transmit or
receive FIFO buffer for SSI_CH0 to SSI_CH5 can be reset separately.
• Transmit suspension
Immediate stop or stop after data transfer in block units can be selected. During transmit
suspension, arbitrary data (for example, silent data) can be automatically transferred to
SSI_CH0 through SSI_CH5.
Rev. 1.00 Nov. 22, 2007 Page 679 of 1692
REJ09B0360-0100