SH7764 Datasheet, PDF (394/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
[Recovery from self-refresh state]
1. Clear the DRE and RMODE bits in MIM to 0 to clear the self-refresh state. Here, the BW[1:0]
bits should be set again.
2. Whether the SDRAM has recovered from the self-refresh state can be checked by reading the
SELFS bit in MIM.
3. After the self-refresh state is cleared, wait for the time required by the SDRAM before
accessing the SDRAM.
4. When access becomes possible, use the SMS[2:0] bits in SCR to issue the CBR (auto-refresh)
command so that the concentrated refresh (CBR) is performed on all memory rows.
5. Use the SMS[2:0] bits in SCR to issue the PALL (precharge select all bank) command.
6. Use the SMS[2:0] bits in SCR to issue the CBR command.
7. Set MIM so that the counter for the auto-refresh function starts counting and thus drives auto-
refreshing at a regular interval. After this, normal memory access is possible.
11.7.9 SDRAM Initialization Sequence
An example of the initialization sequence for the SDRAM is shown below. For details, see each
memory manufacturer's datasheet.
1. Turn on the power supplies to the SDRAM in the order of VDD and VDDQ.
2. After the power supply and clock are stabilized, maintain the current state for at least 200 µs.
3. Set the BW[1:0] and BOMODE[1:0] bits in MIM to enable the SDRAM controller and set the
bus width and SDRAM access mode. Here, the DRE bit should remain 0 to prevent counter
operation from enabling automatic auto-refresh operation.
4. Set the SPLIT[3:0] bits in SDRA to select the appropriate address multiplexing for the type of
memory to be connected. Also set the STR register according to the timing specifications of
the memory to be connected.
5. Use the SMS[2:0] bits in SCR to enable the CKE pin. This drives the external CKE pin high.
6. Use the SMS[2:0] bits in SCR to issue the PALL (precharge select all bank) command.
7. Use the SMS[2:0] bits in SCR to issue the CBR (auto-refresh) command eight times.
8. Use SDMR to issue the MRS command to determine the SDRAM operating mode.
Rev. 1.00 Nov. 22, 2007 Page 338 of 1692
REJ09B0360-0100