SH7764 Datasheet, PDF (342/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Initial
Bit
Bit Name Value R/W
Description
2
ATAM
0
R/W
ATAPI Request Mask Enable
0: ATAPI request is not masked.
1: ATAPI request is masked.
1, 0

All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
Arbitration of memory access can be masked for each module during NMI. The setting of this
register is reflected in the arbitrating operation. Accordingly, it is not applied to the memory
access in progress.
Rev. 1.00 Nov. 22, 2007 Page 286 of 1692
REJ09B0360-0100