SH7764 Datasheet, PDF (502/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.3.17 Interrupt Mask Clear Register 1 (INT2MSKCR1)
INT2MSKCR1 is a 32-bit write-only register that clears any masking set in the interrupt mask
register. Setting bits in this register to 1 clears the masking of the corresponding interrupt sources.
Reading bits in this register is always 0.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
— SCIF2 —
—
—
—
— VDC2 — USB EtherC
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: W W W W W W W W W W W W W W W W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
— _LCDC —
— IIC
—
SRC SRC
ODFI IDEI
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: W W W W W W W W W W W W W W W W
Initial
Bit
Bit Name Value R/W
31 to —
26
All 0
W
25
SCIF2
0
W
24 to —
20
All 0
W
19
VDC2
0
W
18
—
0
W
17
USB
0
W
16
EtherC 0
W
15 to 8 —
All 0
W
7
LCDC
14 to 5 —
0
W
All 0
W
Function
Description
Reserved
Clears interrupt masking
The write value should always ^{for each peripheral}
be 0
module.
Clears SCIF2 interrupt masking ^{[When writing]}
Reserved
0: Invalid
The write value should always
be 0
1: Interrupt mask is
cleared
Clears VDC2 interrupt masking ^{[When reading]}
Reserved
Always 0
The write value should always
be 0
Clears USB interrupt masking
Clears EtherC interrupt
masking
Reserved
The write value should always
be 0
Clears LCDC interrupt masking
Reserved
The write value should always
be 0
Rev. 1.00 Nov. 22, 2007 Page 446 of 1692
REJ09B0360-0100