SH7764 Datasheet, PDF (1498/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 User Break Controller (UBC)
Figure 30.1 shows the UBC block diagram.
Access ^{SDB SAB}
ASID control
Access
comparator
ASID
comparator
Address
comparator
Channel 0
operation
control
CBR0
CAR0
CAMR0
CRR0
Internal bus
Access
comparator
ASID
comparator
Address
comparator
Data
comparator
Channel 1
operation
control
CBR1
CAR1
CAMR1
CDR1
CDMR1
CETR1
CRR1
Control
CCMFR
CBCR
User break is requested.
[Legend]
CBR0: Match condition setting register 0
CRR0: Match operation setting register 0
CAR0: Match address setting register 0
CAMR0: Match address mask setting register 0
CBR1: Match condition setting register 1
CRR1: Match operation setting register 1
CAR1: Match address setting register 1
CAMR1: Match address mask setting register 1
CDR1: Match data setting register 1
CDMR1: Match data mask setting register 1
CETR1: Execution count break register
CCMFR: Channel match flag register
CBCR: Break control register
SAB: Operand address bus
SDB: Operand data bus
Figure 30.1 Block Diagram of UBC
Rev. 1.00 Nov. 22, 2007 Page 1442 of 1692
REJ09B0360-0100