SH7764 Datasheet, PDF (705/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
2
RPTMD 0
R/W Repeat Mode
Selects either normal mode or repeat mode.
0: Normal mode
1: Repeat mode
1
TRMD
0
R/W Transmission/Reception Mode Selection
Selects either transmission mode or reception mode of
SSI_DMAC0/1 of corresponding SSI channel from 0 to
5 (SSI_CH0 to SSI_CH5).
0: Reception mode
1: Transmission mode
0
DMEN
0
R/W SSI-DMAC Enable
Enables or disables the SSI_DMAC0/1 operation of
corresponding SSI channel from 0 to 5 (SSI_CH0 to
SSI_CH5).
0: The SSI_DMAC0/1 operation is disabled.
1: The SSI_DMAC0/1 operation is enabled.
18.3.7 Transmit Suspension Block Counters 0 to 5 (SSISTPBLCNT0 to SSISTPBLCNT5)
SSISTPBLCNT0 to SSISTPBLCNT5 is a 32-bit readable/writable register that set the number of
blocks to be transferred after the TXSTOP0 to TXSTOP5 bits in SSIDMAOR0 and SSIDMAOR1
are set to 1 until the transmit suspension state is entered. This register is decremented after each
one block transfer and enters transmit suspension state when it is decremented to 0. This register
value is initialized when either of the conditions is implemented such as hardware reset, software
reset or software reset for SSI_DMAC (DMRST bit in SSIDMACOR0 to SSIDMACOR3). To be
written to this register, DMEN bit in SSIDMCOR0 to SSDMCOR5 must be 0.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXSTOPBL[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TXSTOPBL[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 649 of 1692
REJ09B0360-0100