SH7764 Datasheet, PDF (1177/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
3. Command Parameters
n (n = 2 to 65,535): Number of vertices
DXn (n = 2 to 65,535): Rendering coordinate (absolute coordinate). Negative number
expressed as two's complement.
DYn (n = 2 to 65,535): Rendering coordinate (absolute coordinate). Negative number
expressed as two's complement.
LINK Address:
LINK absolute address (Longword address. Write 0 to bits A31 to
A29, A1, and A0).
LINK relative address (Longword address. Negative number
expressed as two's complement. Bits A31 to A29 are used to extend
the sign in bit A28. Write 0 to bits A1 and A0.)
Note: Even in 32-bit addressing mode, write the values in bits 28 to 3 of the specified 32-bit
address to bits A28 to A3.
(c) Description
Performs antialiasing for the exterior frame of a polygon drawn using work reference.
The CLKW bit specifies whether the order to give the n vertices is clockwise or counterclockwise:
CLKW = 1 selects clockwise and CLKW = 0 selects counterclockwise. When clockwise is
specified, the left image with respect to the drawing direction is referenced by antialiasing. On the
other hand, the right image is referenced when counterclockwise is selected. When LINKE = 1,
the vertex coordinates are read from the memory address specified by the LINK Address. The
LINK Address can be specified through the LREL bit as an absolute address or a relative address
with respect to the memory address at which the LINED command code is located.
This command can only be executed for a 16-bit/pixel destination.
When a polygon used in work reference is drawn by the FTRAPC (RFTRAPC) command,
perform drawing with both the EDG and EOS bits set to 1.
Rev. 1.00 Nov. 22, 2007 Page 1121 of 1692
REJ09B0360-0100