SH7764 Datasheet, PDF (506/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
Module
Bit
Source Function
Description
DMAC
2
1
0
DMINT2 Channel 2 DMA transfer end/half-end Indicates DMAC
interrupt
interrupt sources. This
DMINT1
Channel 1 DMA transfer end/half-end
interrupt
register indicates DMAC
interrupt sources even if
mask setting is made in
DMINT0 Channel 0 DMA transfer end/half-end the interrupt mask
interrupt
register for them.
INT2B4: Indicates detailed interrupt sources for the SSI.
Module
SSI
Bit
31 to 9
8
7
6
5
4
3
2
1
0
Source Function
Description
—
SSICH5
SSICH4
SSICH3
SSIDMA1
These bits are always read as 0. The
write value should always be 0.
SSI ch5 interrupt
SSI ch4 interrupt
SSI ch3 interrupt
SSI DMA1 interrupt
Indicates SSI interrupt
sources. This register
indicates the SSI
interrupt sources even if
mask setting is made in
the interrupt mask
register for them.
—
These bits are always read as 0. The
write value should always be 0.
SSICH2 SSI ch2 interrupt
SSICH1 SSI ch1 interrupt
SSICH0 SSI ch0 interrupt
SSIDMA0 SSI DMA0 interrupt
Rev. 1.00 Nov. 22, 2007 Page 450 of 1692
REJ09B0360-0100