SH7764 Datasheet, PDF (455/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
Start
Initial settings
(SAR, DAR, TCR, CHCR, DMAOR,
SARB, DARB, TCRB, DMARS)
DE, DME = 1 and
No
TE, AE, NMIF = 0?
*¹
Yes
Transfer request occurs? ^No
Yes
*²
Transfer (1 transfer unit);
TCR – 1 → TCR, SAR, and DAR updated _*6
Reload mode: TCRB[7:0] − 1 → TCRB[7:0]
Reload mode?
No
Yes
No
TCR[7:0] = 0?
Yes
SARB/DARB load
*⁵
TCRB[23:16] → TCRB[7:0] load *⁶
*³
*⁴
Bus mode, DREQ
detection system,
transfer request mode
No
TCR = 0?
Yes
TE = 1
DEI interrupt request
(IE = 1)
No
TCR = TCRB/2?
Yes
HE = 1, DEI interrupt
request (HIE = 1)
Yes
Repeat mode?
NMIF = 1 or AE = 1 or
No
DE = 0 or DME = 0?
No
SARB/DARB load
*⁵
Yes
TCRB → TCR load
NMIF = 1 or AE =1 or
DE = 0 or DME = 0?
Yes
No
HIE = 0 or HE = 1?
No
Yes
Normal end
Transfer end
Notes: 1. In repeat mode, a transfer request is acceptted with TE =1 when HIE = 1 and HE = 0
(half end interrupt is enable and clear the HE to 0 after HE is set to 1).
2. In auto-request mode, transfer starts when bits NMIF, AE, and TE are all 0 or bits TE
and HIE are 1 and HE is 0 (in repeat mode), and bits DE and DME are set to 1.
3. DREQ is level detection (external requesrt) in burst mode or cycle-steral mode.
4. DREQ is edge detection (external request) or auto request in burst mode.
5. Loading to SAR and DAR differs according to the operating conditions in each mode.
Figure 12.11 DMA Transfer Flowchart
Rev. 1.00 Nov. 22, 2007 Page 399 of 1692
REJ09B0360-0100