SH7764 Datasheet, PDF (341/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Initial
Bit
Bit Name Value R/W
63 to 25 
All 0 R
24
NMIME 0
R/W
23 to 17 
All 0 R
16
LCDM
0
R/W
15 to 11 
All 0 R
10
VDCM
0
R/W
9 to 7 
All 0 R
6
2DDM
0
R/W
5
2DCM
0
R/W
4, 3

All 0 R
Section 11 Memory Controller Unit (MCU)
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Request Mask Enable during NMI
0: Main memory access request is not masked when
an NMI occurs.
1: Main memory access request is masked when an
NMI occurs.
Reserved
These bits are always read as 0. The write value
should always be 0.
LCDC Request Mask Enable
0: LCDC request is not masked.
1: LCDC request is masked.
Reserved
These bits are always read as 0. The write value
should always be 0.
VDC2 Request Mask Enable
0: VDC2 request is not masked.
1: VDC2 request is masked.
Reserved
These bits are always read as 0. The write value
should always be 0.
2DD (G2D Data) Request Mask Enable
0: 2DDM request is not masked.
1: 2DDM request is masked.
2DC (G2D Command) Request Mask Enable
0: 2DCM request is not masked.
1: 2DCM request is masked.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Nov. 22, 2007 Page 285 of 1692
REJ09B0360-0100