SH7764 Datasheet, PDF (761/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Name
Automatic PAUSE frame retransmit count register
Random number generation counter upper limit setting
register
PAUSE Frame Receive Counter Register
PAUSE frame retransmit counter register
Broadcast frame receive count setting register
Section 19 Ethernet Controller (EtherC)
Abbreviation
TPAUSER
RDMLR
Software Reset
Initialised
Initialised
RFCF
TPAUSECR
BCFRR
Initialised
Initialised
Initialised
19.3.1 EtherC Mode Register (ECMR)
ECMR is a 32-bit readable/writable register that specifies the operating mode of the EtherC. The
settings in this register are normally made in the initialization process following a reset.
The operating mode setting must not be changed while the transmitting and receiving functions
are enabled. To switch the operating mode, return the EtherC and E-DMAC to their initial states
by means of the SWR bit in EDMR before making settings again.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
— TPC ZPF PFR RXF TXF
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
—
—
— PRCEF —
— MPDE —
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R/W R R R/W R
7
6
5
4
3
2
1
0
—
RE TE
— ILB
—
DM PRM
0
0
0
0
0
0
0
0
R R/W R/W ^R R/W R R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 21 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
20
TPC
0
R/W PAUSE Frame Transmission
0: PAUSE frame is not transmitted in a PAUSE period
1: PAUSE frame is transmitted even in a PAUSE period
Rev. 1.00 Nov. 22, 2007 Page 705 of 1692
REJ09B0360-0100