SH7764 Datasheet, PDF (17/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

14.3.5 Timer Control Registers (TCRn) (n = 0 to 5) ....................................................... 478
14.3.6 Input Capture Register 2 (TCPR2)........................................................................ 480
14.4 Operation ........................................................................................................................... 481
14.4.1 Counter Operation................................................................................................. 481
14.4.2 Input Capture Function ......................................................................................... 484
14.5 Interrupts............................................................................................................................ 486
14.6 Usage Notes ....................................................................................................................... 487
14.6.1 Register Writes ..................................................................................................... 487
14.6.2 Reading from TCNT............................................................................................. 487
14.6.3 External Clock Frequency..................................................................................... 487
Section 15 Serial Communication Interface with FIFO (SCIF) ........................489
15.1 Features.............................................................................................................................. 489
15.2 Input/Output Pins ............................................................................................................... 492
15.3 Register Descriptions ......................................................................................................... 493
15.3.1 Receive Shift Register (SCRSR)........................................................................... 496
15.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 496
15.3.3 Transmit Shift Register (SCTSR) ......................................................................... 497
15.3.4 Transmit FIFO Data Register (SCFTDR) ............................................................. 497
15.3.5 Serial Mode Register (SCSMR)............................................................................ 498
15.3.6 Serial Control Register (SCSCR).......................................................................... 501
15.3.7 Serial Status Register (SCFSR) ............................................................................ 505
15.3.8 Bit Rate Register (SCBRR) .................................................................................. 513
15.3.9 FIFO Control Register (SCFCR) .......................................................................... 518
15.3.10 FIFO Data Count Set Register (SCFDR) .............................................................. 521
15.3.11 Serial Port Register (SCSPTR) ............................................................................. 522
15.3.12 Line Status Register (SCLSR) .............................................................................. 525
15.3.13 Serial Extension Mode Register (SCEMR)........................................................... 526
15.4 Operation ........................................................................................................................... 527
15.4.1 Overview............................................................................................................... 527
15.4.2 Operation in Asynchronous Mode ........................................................................ 530
15.4.3 Operation in Clock Synchronous Mode................................................................ 541
15.5 SCIF Interrupts .................................................................................................................. 549
15.6 Usage Notes ....................................................................................................................... 550
15.6.1 SCFTDR Writing and TDFE Flag ........................................................................ 550
15.6.2 SCFRDR Reading and RDF Flag ......................................................................... 550
15.6.3 Break Detection and Processing ........................................................................... 551
15.6.4 Sending a Break Signal......................................................................................... 551
15.6.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 551
15.6.6 Selection of Base Clock in Asynchronous Mode.................................................. 553
Rev. 1.00 Nov. 22, 2007 Page xvii of lvi