SH7764 Datasheet, PDF (141/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 4 Pipelining
4.3 Issue Rates and Execution Cycles
Instruction execution cycles are summarized in table 4.4. Instruction Group in the table 4.4
corresponds to the category in the table 4.2. Penalty cycles due to a pipeline stall are not
considered in the issue rates and execution cycles in this section.
1. Issue Rate
Issue rates indicates the issue period between one instruction and next instruction.
E.g. AND.B instruction
I1
I2
I3
ID
S1
S2
S3 WB
ID
ID E1S1 E2S2 E3S3 WB
Issue rate: 3
Next instruction _{(I1) (I2) (I3) (ID)}
E.g. MAC.W instruction
I1
I2
I3
ID S1
S2
S3 WB
ID
S1
S2 S3 WB
Issue rate: 2
M2 M3 MS
Next instruction (I1) (I2) (I3) (ID)
2. Execution Cycles
Execution cycles indicates the cycle counts an instruction occupied the pipeline based on the next rules.
CPU instruction
E.g. AND.B instruction
I1
I2
I3
ID S1
ID
Execution Cycles: 3
S2 S3 WB
ID E1S1 E2S2 E3S3 WB
E.g. MAC.W instruction
I1
I2
I3
FPU instruction
E.g. FMUL instruction
I1
I2
I3
Execution Cycles: 4
ID S1 S2 S3 WB
ID
S1
S2
S3 WB
M2 M3 MS
Execution Cycles: 3
ID FE1 FE2 FE3 FE4 FE5 FE6 FS
FE1 FE2 FE3 FE4 FE5 FE6 FS
FE1 FE2 FE3 FE4 FE5 FE6 FS
E.g. FDIV instruction
I1 I2 I3
ID FE1 FE2 FE3 FE4 FE5 FE6 FS
Divider occupation cycle
Execution Cycles: 14
FE3 FE4 FE5 FE6 FS
Rev. 1.00 Nov. 22, 2007 Page 85 of 1692
REJ09B0360-0100