SH7764 Datasheet, PDF (549/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 15 Serial Communication Interface with FIFO (SCIF)
15.3 Register Descriptions
Figure 15.2 shows the SCIF register configuration. Figure 15.3 shows the register states in each
processing mode. Since the register functions are the same in each channel, the channel number is
omitted in the description below.
Table 15.2 Register Configuration
Channel Register Name
Abbreviation R/W
Area 7
P4 Address Address
Access
Size
0
Serial mode register_0
SCSMR_0
R/W H'FFE0 0000 H'1FE0 0000 16
Bit rate register_0
SCBRR_0
R/W H'FFE0 0004 H'1FE0 0004 8
Serial control register_0
SCSCR_0
R/W H'FFE0 0008 H'1FE0 0008 16
Transmit FIFO data register_0 SCFTDR_0
Serial status register_0
SCFSR_0
W
H'FFE0 000C H'1FE0 000C 8
R/(W)*¹ H'FFE0 0010 H'1FE0 0010 16
Receive FIFO data register_0 SCFRDR_0 R
H'FFE0 0014 H'1FE0 0014 8
FIFO control register_0
SCFCR_0
R/W H'FFE0 0018 H'1FE0 0018 16
FIFO data count register_0 SCFDR_0
R
H'FFE0 001C H'1FE0 001C 16
Serial port register_0
Line status register_0
SCSPTR_0
SCLSR_0
R/W H'FFE0 0020 H'1FE0 0020 16
R/(W)*² H'FFE0 0024 H'1FE0 0024 16
Serial extension mode
register_0
SCEMR_0
R/W H'FFE0 0028 H'1FE0 0028 16
1
Serial mode register_1
SCSMR_1
R/W H'FFE1 0000 H'FE1 0000 16
Bit rate register_1
SCBRR_1
R/W H'FFE1 0004 H'FE1 0004 8
Serial control register_1
SCSCR_1
R/W H'FFE1 0008 H'FE1 0008 16
Transmit FIFO data register_1 SCFTDR_1
Serial status register_1
SCFSR_1
W
H'FFE1 000C H'FE1 000C 8
R/(W)*¹ H'FFE1 0010 H'FE1 0010 16
Receive FIFO data register_1 SCFRDR_1 R
H'FFE1 0014 H'FE1 0014 8
FIFO control register_1
SCFCR_1
R/W H'FFE1 0018 H'FE1 0018 16
FIFO data count register_1 SCFDR_1
R
H'FFE1 001C H'FE1 001C 16
Serial port register_1
Line status register_1
SCSPTR_1
SCLSR_1
R/W H'FFE1 0020 H'FE1 0020 16
R/(W)*² H'FFE1 0024 H'FE1 0024 16
Serial extension mode
register_1
SCEMR_1
R/W H'FFE1 0028 H'FE1 0028 16
Rev. 1.00 Nov. 22, 2007 Page 493 of 1692
REJ09B0360-0100