SH7764 Datasheet, PDF (484/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.3.8 User Interrupt Mask Level Register (USERIMASK)
USERIMASK is a 32-bit readable and writable with conditions register that sets the acceptable
interrupt level. When addresses in area 7 are accessed using the MMU address translation
function, USERIMASK can be accessed in user mode. Since only USERIMASK is allocated in
the 64-Kbyte page (other INTC registers are allocated to a different area), it can be set to be
accessed in user mode.
Interrupts whose priority levels are lower than the level set in the UIMASK bit are masked. If the
value of H'F is set to the UIMASK bit, all interrupts other than the NMI are masked.
Interrupts whose priority levels are higher than the level set in the UIMASK bit are accepted under
the following conditions:
• The corresponding interrupt mask bit in the interrupt mask register is cleared to 0 (the interrupt
is enabled).
• The priority level set in the IMASK bit in SR is lower than that of the interrupt.
Even if interrupts are accepted, the UIMASK value is not changed.
USERIMASK is initialized to H'0000 0000 (all interrupts are enabled) when returning from a
power-on reset.
To prevent incorrect writing, this register can only be written to with bits 31 to 24 set to H'A5.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7

6
5
UIMASK
4
3
2
1
0

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R R R R
Rev. 1.00 Nov. 22, 2007 Page 428 of 1692
REJ09B0360-0100