SH7764 Datasheet, PDF (1087/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 22 LCD Controller (LCDC)
Bit
7 to 4
3 to 0
Bit Name
OFFE[3:0]
OFFF[3:0]
Initial Value R/W
0000
R/W
1111
R/W
Description
LCDC Power-Off Sequence Period
Set the period from LCD_VEPWC negation to
stopping output of the display data (LCD_D) and
timing signals (LCD_FLM, LCD_CL1, LCD_CL2,
and LCD_M_DISP) in the power-off sequence of the
LCD module in frame units.
Specify to the value of (the period)-1.
This period is the (e) period in figures 22.4 to 22.7,
Power-Supply Control Sequence and States of the
LCD Module.
LCDC Power-Off Sequence Period
Set the period from stopping output of the display
data (LCD_D) and timing signals (LCD_FLM,
LCD_CL1, LCD_CL2, and LCD_M_DISP) to
LCD_VCPWC negation to in the power-off
sequence of the LCD module in frame units.
Specify to the value of (the period)-1.
This period is the (f) period in figures 22.4 to 22.7,
Power-Supply Control Sequence and States of the
LCD Module.
Rev. 1.00 Nov. 22, 2007 Page 1031 of 1692
REJ09B0360-0100